FIG. 1 shows a multiport cell SRAM 150 that has true/complement pairs of wires that form bit line pairs or ports. The multiport cell SRAM 150 includes MNTT (true side pass component), MPLT (true load transistor), MPLC (complement side load transistor), MNDT (true side drive transistor), MNDC (complement side drive transistor), MNTC (complement side pass component), W0 (word line topside), W1 (word line bottom), B0t (true side bit line 1), B1T (true side bit line 2), B0C (complement side bit line 1) and B1C (complement side bit line 2). Referring to FIG. 1, transistors MPLT, MPLC, MNDT and MNDC constitute the data holding portion of SRAM memory cell 150. Transistors MNTT and MNTC are pass gates.
Read stability and writeability are parameters that are used to assess the operation of memory cells. SRAM cells are considered stable if they can be read without the read operation causing the state of the data that is stored within them to change. As regards reads, during a read operation, turning on the pass gates, which are controlled by the word lines, results in a beta ratio effect on the low side of the memory cell between MNTT and MNOT. The increasing voltage on node MT turns on MNDC and causes a lowering of the voltage on node MC. A size ratio must be utilized as a part of the design implementation that prevents a feedback to node MT which would be positively reinforcing (causing read instability). Typical ratios of WMNDT/WMNTT=WMNDC/WMNTC of approximately 2 are considered good design practice.
As regards writes, during write operations one of the pair of bit lines is transitioned low (Vss). An internal change of state results from the low bit line pulling the high node toward Vss (current Ids flows through transfer gate MNTC) and is assisted by the MNTT gate pulling MT up toward Vdd. The MNTC MOSFET gate must have sufficient current to pull the high node lower (MPLC is acting like a resistor in the linear region of MOSFET operations). The voltage drop across the MPLC must be high enough to induce unstable feedback to change state. Process statistical variability can result in weak N/strong P conditions which can result in the inability to write. Ratioed memory cells can exhibit difficulty at lowered Vdd supply.
FIG. 2 shows another conventional multiport SRAM memory cell 250. SRAM memory cell 250 includes data storage and pass components similar to those shown in FIG. 1. In addition to components shown in FIG. 1, SRAM memory cell 250 includes separate read transistors that are coupled to separate read word lines Rwl0 and Rwl1 (these word line a separate from write word lines Wwl0 and Wwl1). Transistors MNTT and MNTC are pass gates. SRAM memory cell 250 features separate read and write ports (as part of a so called 8T cell) that improves writeability and provides low Vdd functionality. As regards readability, read operations do not activate transistors that are connected to internal nodes, i.e. only gate connections resulting in minimal read disturbance of internal storage nodes. Typically, for “single ended” reads, true/complement bit lines are not relevant for stability. As regards writeability, writes are improved since transistors can be beta ratioed to favor writes since activation of a write word line implies a state change is intended (contrast to shared port cell).
FIG. 1 shows a multiport cell SRAM 150 that has true/complement pairs of wires that form bit line pairs or ports. The multiport cell SRAM 150 includes MNTT (true side pass component), MPLT (true load transistor), MPLC (complement side load transistor), MNDT (true side drive transistor), MNDC (complement side drive transistor), MNTC (complement side pass component), W0 (word line topside), W1 (word line bottom), B0t (true side bit line 1), B1T (true side bit line 2), B0c (complement side bit line 1) and B1C (complement side bit line 2). Referring to FIG. 1, transistors MPLT, MPLC, MNDT and MNDC constitute the data holding portion of SRAM memory cell 150. Transistors MNTT and MNTC are pass gates.
Disadvantages of SRAM memory cell 250 is that multiple separate write/read wordline wires are required and separate write/read bit lines (ports) are used. Area usage is high due to large number of wire pitches. Active transistors are also high due to separate active area for read and write transistors.
Increasing the memory cell density of memory cell arrays increases the data storage capacity of memory cell arrays. Many conventional designs feature port intensive memory cell structures. Such structures are implemented using increased numbers of wires/lines (e.g., bit lines and word lines) that increase power consumption and require more area. In addition, some conventional designs utilize more transistors that also require more area.